SDRAM timing issues

The timing of SDRAM focuses on three times:

CL=2: CAS Latency, CAS latency, CAS and read command issued to the first data output time ---- read operation
tRCD=2: RAS to CAS Delay, the delay time of the address after the row address is sent ---- the row and column address delay
tRP=2: Close the existing work line, ready to open a new line, after a period of time to allow the RAS line to send a valid command to open a new work line ---- Precharge time
OK, all three times are clear.

In the external interface, the row address and column address multiplexing mode is adopted, and two interfaces are added for this: row address strobe RAS, column address strobe CAS. tRCD (typically 2-3 cycles) is the latency between the row strobe RAS and the column strobe CAS, and CL is the delay from the column address strobe to the first data read (typically 2-3 cycles) ,

DDR is from SDRAM. Strictly speaking, it should be called DDR SDRAM. DDR SDRAM is the abbreviation of Double Data Rate SDRAM. It is the meaning of double rate synchronous dynamic random access memory. Therefore, there is a big part, the two are the same, understand SDRAM, Then come to understand the improvement of DDR on SDRAM, the effect should be better, here to thank the great god of Chinaunix.net - Tekkaman Ninja, my memory learning materials areTekkaman Ninja's blogIntroduced in the introduction. The following is some personal finishing of my recommendation document for Great God, OK, first a structure diagram of SDRAM.

Below is a simple SDRAM work flow chart I drew

The red number in the picture is the main time we need to find, and now we are starting to look at the picture.
1. Chip initialization
The SDRAM chip has a logic control unit inside and a mode register to provide control parameters. Therefore, SDRAM must first initialize this control logic core each time it is turned on.

2. Line is valid
After initializing, to address an array in an L-Bank, first determine the row (Row), make it active (Active), and then determine the column. . Simply understand the first pass address.

3. Column read and write
After the row address is determined, the column address is addressed. The read and write signals and column addresses are sent at the same time. The operation of reading and writing depends on the WE# pin. When it is enabled, it is written, otherwise it is read.
in the send columnThere must be an interval between the read and write commands and the line valid commands. This interval is defined as tRCD, which is RAS to CAS Delay. You can also understand the line strobe period. Simple understanding means that After the address is sent, when the address and read/write signals are sent, it needs to be delayed. This should be based on the delay of the chip storage array electronic component response time (the process from one state to another).
The generalized tRCD is in units of clock cycles (tCK, Clock Time). For example, tRCD=2 means that the delay period is two clock cycles. To the exact time, it depends on Depending on the clock frequency, for PC100 SDRAM, tRCD=2 represents a delay of 1000/100 * 2 = 20ns, and the figure below is a timing diagram of tRCD=3.

4. Data output (read)
After the column address is selected, the specific memory location has been determined. The only thing left is that the data is output to the memory bus through the data I/O channel (DQ).
However, after the CAS is issued, it still takes a certain period of time to have data output. The time from the CAS and the read command to the first data output is defined as CL (CAS Latency, CAS latency). Since CL appears only when reading, CL is also called read latency (RL, Read Latency), and the figure below is a schematic diagram of CL=2.。

5. Data input (write)
The data write operation is also performed after tRCD.But there is no CL at this time (remember, CL only appears in the read operation),The timing diagram for row addressing and column addressing is the same as above, except that in column addressing, WE# is active.
In order to ensure reliable writing of data, sufficient write/correction time (tWR, Write Recovery Time) is left.The operation is also called Write Back. tWR takes at least one clock cycle or a little more (the higher the clock frequency, the more tWR cycles)
 

6.Burst Lengths

Burst meansMethod of continuously transmitting data between adjacent storage units in the same row，Continuous transmission involves storageThe number of storage units (columns) is the Burst Lengths (BL).

As long as the starting column address and burst length are specified, the memory will automatically perform read/write operations on the corresponding number of subsequent memory cells in turn without the need for the controller to continuously provide column addresses. Thus, except that the transmission of the first data requires several cycles (mainly the previous delay, typically tRCD+CL), each data can be obtained in only one cycle.

7. Precharge
Since the addressing of SDRAM is specific, it is effective (working) if you want to address another row of the same bank after reading and writing. The line is closed and the row/column address is resent. Bank closes the existing work line, and the operation to open a new line is precharge.
After the precharge command is issued, it takes a period of time to allow the RAS line valid command to open a new work line. This interval is called tRP (Precharge command Period). . Like tRCD and CL, the unit of tRP is also the number of clock cycles, depending on the clock frequency.

8. Refresh
is called DRAM because it keeps refreshing to retain data, so it is the most important operation of DRAM. The refresh operation is the same as the rewrite operation in precharge, which is read and rewritten with S-AMP.
But why do you need to refresh the precharge operation? Because precharge is a work line operation in one or all L-Banks, and it is irregular, and refresh has a fixed period, and all rows are operated in order to retain those banks that have not undergone rewriting for a long time. The data in . However, unlike all L-Bank precharges, the row here refers to the same address in all L-Banks, and the work row addresses in each L-Bank in precharge are not necessarily the same. For example, I have four pieces. The refresh is that I refresh one of the four memory addresses and then the next one; the precharged work line address can be different.
So how often do you want to refresh again? The currently accepted standard is that the effective data retention period of the capacitor in the bank is 64ms (milliseconds, 1/1000 second), which means that the refresh cycle of each row is 64ms. This refresh rate is: the number of rows / 64ms. When we look at the memory specifications, we often see the 4096 Refresh Cycles/64ms or 8192 RefreshCycles/64ms flags, where 4096 and 8192 represent the number of rows per L-Bank in the chip. The refresh command is valid for one line at a time, and the transmission interval varies with the total number of lines, which is 15.625 μs (microseconds, 1/1000 milliseconds) for 4096 lines and 7.8125 μs for 8192 lines.
There are two types of refresh operations: Auto Refresh (AR) and Self Refresh (SR).
SR is mainly used for data storage in sleep mode low power state. The most famous application in this aspect is STR (Suspend to RAM). When the AR command is issued, CKE is put into an invalid state, and the SR mode is entered. At this time, the system clock is no longer operated, but the refresh operation is performed according to the internal clock. All external signals except CKE are invalid during SR (no external refresh command is required), and only when CKE is valid again can the self-refresh mode be exited and the normal operation state is entered.
 

The above is the main working steps of SDRAM. Comparing the simple working flow chart at the top, is the time clear?

CL=6: CAS Latency, CAS latency, CAS and read command time to the first data output ---- Read operation
tRCD=6: RAS to CAS Delay, the delay time of the address after the row address is sent ---- the row and column address delay
tRP=6: Close the existing work line, ready to open a new line, after a period of time to allow the RAS line to send a valid command to open a new work line ---- pre-charge time
OK, all three times are clear.